Over the last decades, bandwidth scaling in datacenters and supercomputers have pushed the need for high-speed short-reach optical interconnects. Low cost and energy efficiency are of interest, which makes the 850 nm wavelength directly modulated vertical cavity surface-emitting lasers (VCSELs) one solution for board-to-board and chip-to-chip connections in supercomputing systems and datacenters. Recently, significant improvements have been demonstrated in the performance of an 850 nm VCSEL for 50 Gb/s and beyond. High-speed, power efficient and high bandwidth density VCSEL-based short-reach optical interconnects with a hybrid integration of a photodetector have been demonstrated in the literature.
Silicon with high absorption coefficient at short wavelengths enables monolithic integration of an optical receiver with a photodetector. This integration reduces the cost and complexity of the packaging and provides a more reliable optical system. The combination of a low cost and power efficient 850 nm VCSEL with the monolithic integration of a silicon photodetector (Si-PD) and an optical receiver fabricated in a cost-effective, mature, and highly reliable complementary metal-oxide-semiconductor (CMOS) technology could be a cost-effective solution for short-reach optical interconnects.
FIG. 1 shows an example of a p-n Si-PD in a conventional bulk CMOS technology. Since the penetration depth of the 850 nm light in bulk silicon is larger than 10 μm, most of the photons are absorbed outside the depletion region. The slow diffusion current of carriers generated outside the depletion region limits the speed of the Si-PD to sub-GHz in bulk technology. Several techniques have been demonstrated to reduce the slow diffusion of carriers in Si-PDs at the cost of responsivity degradation. Most of the existing Si-PDs are designed for avalanche performance (avalanche photodetector (APD)) to increase the responsivity in the modified Si-PDs. However, to the inventors' knowledge, the maximum bandwidth reported of a Si-PD fabricated in a bulk CMOS technology is 12 GHz with a responsivity of 0.03 A/W and an avalanche gain of 10.6 at 9.7 V reverse-bias voltage.
The bandwidth of the Si-PD can be improved further by fabricating the photodetector on a silicon-on-insulator (SOI) platform. An example of a structure of a p-i-n Si-PD in a SOI technology is shown in FIG. 2. Elimination of the diffusion current by using the insulator between the active area of the Si-PD and the substrate improves the bandwidth of the PD without any equalization techniques. However, the responsivity of this type of PD is limited by the thickness of the silicon on the insulator. For instance, in the case of a 210-nm silicon layer, more than 98% of the vertically incident light passes through the silicon and limits the responsivity of the Si-PD to 0.0075 A/W. There thus remains room for improvement.